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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Register values over Serial Lite III

I have 2 FPGAs connected over a Multi-Gigabit Serial Lite III interface.

In addition to the high data rate communications I need to transfer register values between the FPGAs - with one of them being the Master and the other the Slave. For example. lighting an LED that's connected to the Slave FPGA via a register value that's sent from the Master over Serial Lite III to the Slave.

As an option, I can design my own custom message protocol that's layered on-top of the Serial Lite III and allocates a minor portion of the bandwidth for control functions. But I'd like to avoid that and use something native...

So is there a native Intel IP that does that ?

Something like an "Avalon MM Lite extender" on top of Serial Lite III

8 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor

    Hi shaiko,


    May I know that you use which FPGA in this case?


    Best regards,

    Zi Ying


  • host's avatar
    host
    Icon for Occasional Contributor rankOccasional Contributor

    Hello,

    This doesn't answer my question - I couldn't find any helpful information in the link.
    Do you understand what I want to achieve ?

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor

    Hi Shaiko,


    Can I understand your question as you want know which native PHY IP that can support for the 2 FPGAs connected over a Multi-Gigabit Serial Lite III interface?


    Best regards,

    Zi Ying


  • host's avatar
    host
    Icon for Occasional Contributor rankOccasional Contributor

    No. I don't have a doubt that the Arria 10 and Stratix 10 will be able to communicate over Serial Lite III.

    What I'm asking is: Does Altera offer a native interface to transfer register values over Serial Lite III like I illustrated in the above diagram.

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      Hi,
      I don't see a provision for a sideband channel in Serial Lite III interface. You need to insert sideband data in the stream workload.
  • host's avatar
    host
    Icon for Occasional Contributor rankOccasional Contributor

    Thanks for your input.
    The competition does seem to have something like that in the form of the AXI C2C. So I thought Intel has something similar.