Forum Discussion

SnehaRao's avatar
SnehaRao
Icon for New Contributor rankNew Contributor
5 years ago

Regarding maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board

This question is regarding the maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board.

We did the following tests:

A) Using the streaming_dma_afu example for bandwidth. - 6.7 GBps read, 7.6 GBps write
B) Using the nlb_mode_0 example in LPBK1 mode. - 9 to 9.5 GBps
C) Using OpenCL based 'aoc diagnose all'. - 8.4 GBps

Could someone please let us know why the achievable bandwidth in these tests is almost half of the official specification?

6 Replies

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi SNEHA

    May you guide us on which part of the official specification doc you are referring to? Thanks.

    Eng Wei

    • SnehaRao's avatar
      SnehaRao
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi !

      The datasheet of D5005 card (link here, go to pg 3 of 29) specifies it is a PCI Express Gen 3 x16 compliant card. According to the specification of PCI Express, Gen 3 x16 should give bandwidth of 15.75 GB/s (source here). However we are unable to achieve it.

      Regards

      Sneha

      • EngWei_O_Intel's avatar
        EngWei_O_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        Hi SNEHA

        The spec you are mentioning here is the ideal case for a PCIE transfer rate. The testing you are doing involve the overhead of data transfer from host to FPGA and back to host. We can't compare both the numbers.

        Thanks.

        Eng Wei