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SnehaRao's avatar
SnehaRao
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5 years ago

Regarding maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board

This question is regarding the maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board. We did the following tests: A) Using the streaming_dma_afu example for bandwi...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi SNEHA

May you guide us on which part of the official specification doc you are referring to? Thanks.

Eng Wei

  • SnehaRao's avatar
    SnehaRao
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    5 years ago

    Hi !

    The datasheet of D5005 card (link here, go to pg 3 of 29) specifies it is a PCI Express Gen 3 x16 compliant card. According to the specification of PCI Express, Gen 3 x16 should give bandwidth of 15.75 GB/s (source here). However we are unable to achieve it.

    Regards

    Sneha

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
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      5 years ago

      Hi SNEHA

      The spec you are mentioning here is the ideal case for a PCIE transfer rate. The testing you are doing involve the overhead of data transfer from host to FPGA and back to host. We can't compare both the numbers.

      Thanks.

      Eng Wei

      • SnehaRao's avatar
        SnehaRao
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        5 years ago

        Hi!

        Thank you for your response. I agree that data transfer from host to FPGA and then back to host involves some overhead and thus the specified bandwidth cannot be reached. However, could you kindly let us know what is the practically achievable maximum bandwidth via PCIe (v3, x16) for d5005 board (considering the overhead)? And, how to achieve it? It would be of great help to us.

        Thank you

        Regards

        Sneha