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Fpga_Egr_2025's avatar
Fpga_Egr_2025
Icon for Occasional Contributor rankOccasional Contributor
4 months ago
Solved

Gate Level Simulation

Hi , I am trying to run gate level simulation for my uart implementation, but for some reason the Questasim complains about UUT binding not correct . Although in RTL simulation it works fine. See b...
Fpga Devkit
  • RichardT_altera's avatar
    RichardT_altera
    3 months ago

    Hi OP,

    Hopefully, the example code provided in the github is sufficient as a reference to run the gate-level simulation successfully.

    With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you and have a great day!

    Best Regards,

    Richard Tan

AlanCLTan's avatar
AlanCLTan
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hi,

Could you try an experiments to see if it solves the error:

1. Remove the generic entity declaration, including GPIO_WIDTH, from the component declaration?

component UART_Top
port (
-- your ports here
);
end component;

----------------------------------

Remove the generic map from the instantiation?

UUT: UART_Top
port map(
-- your port mappings
);

----------------------------------

Best regards,

Alan Tan