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Chandrashekhar_K's avatar
Chandrashekhar_K
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2 years ago

Cyclone V SoC DDR3 Not working

On custom board we are trying to make the DDR3 up. I'm trying to debug the preloader and check the DDR3 working. Have generated handoff files from Quartus prime. Compiled using BSP editor setting...
Fpga Devkit
Chandrashekhar_K's avatar
Chandrashekhar_K
Icon for New Contributor rankNew Contributor
2 years ago

We were able to resolve the issue and the DDR3 is working now.

The BELSEL pins are set to boot from QSPI. There was no valid image in QSPI and after connecting the JTAG to debug the preloader, we were able to observer the Chip Select pin kept on asserting. (I understand the JTAG should take priority and CS assertion should stop).

We flashed some image and then could observe the CS pin not asserting after connecting JTAG. Still we were not able to make the DDR up in debug mode.

Finally disabled the semihosting feature and enabled the serial support in bsp editor and flashed the compiled u-boot spl image to QSPI We were able to see the the ddr3 being calibrated message in teraterm

After this we were able to debug the preloader with semihosting enabled.

Still not clear with the points

1. The start address the CV Soc kit shows when loading the spl and custom board are different. I think it should be same as the start address after reset will be same for the HPS core.

2. Why there should be some image in boot device to debug the preloder?

3. Why CS keeps asserting even after connecting JTAG without a valid image in it.