Quad SPI flash IO Voltage

Adding more details

- CS, CLK, DATA0, DATA1 - 2.5 VDC level

- DATA2, DATA3 - 3.3 VDC level

Hi there,

Is your device is Cyclone 10 LP or Cyclone 10 GX?

Since the configuration pin of the Cyclone 10 GX is powered by Vccpgm during configuration, I think your device is Cyclone 10 LP.

For Cyclone 10 LP device, the configuration voltage should be 3.3V or 3.0V based on your MSEL settings.

Please refer to the device handbook 6.3.1. MSEL Pin Settings.

https://www.intel.com/content/www/us/en/docs/programmable/683777/current/msel-pin-settings.html

and the KDB for VCCIO in bank 1:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074744.html

Thanks,

Ethan

Thanks Ethan for your reply.

Yes its Cyclone 10 LP device. I needed Bank 1 on 2.5VDC as I have true LVDS lines from that Bank.

Can I have voltage level translator 2.5 to 3.3VDC on IO lines to SPI flash? will that work?

Cheers.

If you use Vccio 2.5V for bank 1 and add a voltage translator between flash and FPGA IO, it would be OK for the hard ware.

But since we do not suggest to configure by this way, I am not sure if there could be any other configuration issue, timing or compile errors.

I suggest to use the 2.5V IOs in the other banks and leave the bank 1 as 3.3V powered.

Thanks,

Ethan

Thank Ethan.