Forum Discussion
Honored ContributorProblems uploading flash memory -- part 2
Hi,
I used the Nios II EDS sof2flash program in the Quartus II 9.1 License Edition to convert a sof file to flash format. I attempted to use the Board Update Portal and the Nios II EDS to program the flash memory with the flash file on my Stratix IV GX FPGA development board (device EP4SGX230KF40C2N). After the file loads 100% successfully into the flash memory, I turn the rotary switch (SW2) on the board from position 0 to 1, then power cycle the board, but an error occurs and red LED D27 comes on. I tried again to program the flash memory and when complete, I pressed the CONFIGN button (S1), but I still get the same error. By the way, the sof file is targeted to my specific device and the Mega Cores used in this sof file are all fully licensed. But we noticed that the size of the flash file created by Nios II EDS is 28 MB and the User Hardware portion of the flash memory is only 12MB. Looks like we're getting this error because I'm trying to make fit a flash file that's too large for the allotted memory space? How do I reduce the size flash file created by Nios II? Thanks, Eric ------------------------------------------------------- Electronics Engineer Microwave and Communication Systems Branch NASA Goddard Space Flight Center, Code 567 8800 Greenbelt Road, Greenbelt, Maryland 20771, USA Building 25, Room S054, Mail Code 567.3 Phone: (301)-286-3439 Email: [email protected] -------------------------------------------------------29 Replies
Altera_ForumDid you use the "--compress" flag when running "sof2flash"? Compressed bitstreams are usually significantly smaller than uncompressed.
Jake- Altera_Forum
I have the same problem with the StratixIV GX Development Board and QuartusII 9.1. While trying to do the board recovery process, I discovered that there is an errata in the file "altera\91\kits\stratixIVGX_4sgx230_fpga\factory_recovery\build_factory_source\build_factory_readme.txt". It says:
Problem Description: The release of Nios II EDS 9.1 tool "sof2flash" does not include support for Stratix IV GX . Work-around: ..... The described the procedure, but the 9.1.0 kit that I have does not have the required file "s4gx230_pfl_programming.sof" required to do parallel programming. I submitted an SR and the response confirmed that this is a bug in 9.1. I have updated my SR to request the "s4gx230_pfl_programming.sof" file. With respect to the .flash file size, the .flash file is in the SREC format which has a text based representation of the binary image. My experience is that this will be over twice as large as the actual binary image. - Altera_Forum
I had the same issue with Arria II GX development board and Quartus II 9.1 software. It looks like there is an issue with 9.1 software. Try using 9.0 SP2 it might work. If you want to load a new design try this procedure:
1. Program the FPGA with the PFL program that comes with the dev kit. Since I am using Arria II GX my factory default SOF file is located in C:\altera\90\kits\arriaIIGX_2agx125es_fpga\factory _recovery\build_factory_source\a2gx_pfl_programmin g.sof. I am hoping you will have a similar file for Stratix IV dev kit after you install the kit installation from the following website http://www.altera.com/products/devki...it-siv-gx.html (http://www.altera.com/products/devkits/altera/kit-siv-gx.html). 2. Create the POF file for the flash using Quartus 9.0 SP2, as 9.1 did not work for me. Use the COF in the same directory that is mentioned in step 1 for creating the POF file. Update only the user SOF file and leave the factory default SOF file. 3. Open Quartus programmer. Click the auto detect button which will show the complete chain. Right click on CFI_<SIZE> and change file to the POF that was created in step 2. Program the USER page(in my case it is page 1, and I think it will be the same for you) of the flash only and do a power cycle. You program will be loaded in the user space of the flash. 4. You might need to move some switch in the board to a particular position to load the user code. Refer to the reference manual of the card for more help on the switch. Hope this helps. - Altera_Forum
The "--compress" flag didn't work for us.
Thanks - Altera_Forum
Well truly it looks like the thing to do is to get Altera to fix it. Let me call some people.
Jake - Altera_Forum
Hi Jake,
I have mentioned about this issue to an Arrow FAE and he has sent a request to Altera. Hopefully Altera will fix this issue in their next service pack. Kumaran - Altera_Forum
If you just want to download your sof into flash, just use Quartus programmer rather than using sof2flash and nios2-flash-programmer. Those program does have issue in 9.1
Just create PFL only FPGA design and download via FPGA. I think the sof area for user is 0x00C20000, don't forget to set the PFL option bit set to 0x18000 - Altera_Forum--- Quote Start --- Well truly it looks like the thing to do is to get Altera to fix it. Let me call some people. Jake --- Quote End --- Thanks Jake and Kumaran. I have submitted an Altera service request 10742901. Nekojitu, I'm working on this now! Thanks, Eric
- Altera_Forum
I will try and fix it myself tomorrow. However, here is response from Altera's NIOS II specialist:
--- Quote Start --- It looks like this is all resolved in SP1 ( not sure exactly when that is coming out but it is soon. I will let you know when I find out. ) If you need it before sp1 there are 2 patches you can request by filing an SR Again, it's patch 0.63 and patch 0.73. --- Quote End --- Jake - Altera_Forum
Oh I should clarify. One of these patches fixes the problem with generating compressed files for Cyclone III. The other deals with the sof2flash support for Stratix IV GX.
Jake
