OpenCL 19.3 SD Card image for Intel Arria 10 Development Kit

Hi,

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf stated: "The handoff settings are output from the Intel Quartus Prime Standard Edition compilation and are located in the / hps_isw_handoff/ directory (where is the HPS component name in Platform Designer (Standard)). You must update the hardware handoff files and regenerate the BSP each time a hardware change impacts the HPS, such as after pin multiplexing or pin assignment changes."

The handoff folder should be there when you compile the qsys which contains the HPS component, I would like to know whether the .qsys file have HPS component?

Thanks

Hi,

No there is no folder or subfolder called "hps_isw_handoff" in the base compile (the same directory where base.qdb or board.qsys resides). I have tried to open the board.qsys with Platform Designer, and from there generate the HDL files, still without luck. The board.qsys file does contain the "Hard Processor System Intel Arria 10 FPGA IP" (altera_arria10_hps).

Hi,

The handoff folder should be available after you fully compile the quartus according to https://rocketboards.org/foswiki/Documentation/A10GSRDCompilingHardwareDesignLTS by clicking >-compiling hardware design as mentioned "~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree "

For the kernel driver, I am checking internally with kernel developer.

Thanks

Hi,

If I need to compile with Quartus, then I need a license right? I had one, but it expired in 2018 and I haven't had any use for the board until recently. Is there any way to invoke Quartus without a license? I.e. is there any way to start the compilation with aoc, where it will use the newly generated HDL files from Platform Designer? or should I look into renewing the Quartus license?

Regarding the driver: perfect!

Hi,

For the OpenCL SDK , you do not need the license file.

For the Quartus, you need a license file for the compilation.

Thanks

Hi,

There is an update for kernel driver from kernel developer. It seems like the locked parameter was added into the Linux kernel to make it compatible with get_user_pages_unlocked/get_user_pages_locked functions. If you pass in NULL to *locked for get_user_pages_remote() function, then it should be safe and behave like the old version.

Thanks

Hi,

It looks like the compiles without any errors, after adding NULL. Now there is only a warning:

a10soc_driver/aclsoc_dma.c:395:3: warning: statement with no effect [-Wunused-value]
   do_exit;
   ^~~~~~~

do_exit is a function. Should it be called, or should it just be ignored?

Is there any way to compile the modified base design using aoc (I.e. the OpenCL SDK)? I am also looking into refreshing our Quartus license for the board.

Hi,

For question regarding the warning and do_exit, I will need to check internally with kernel developer.

For method to compile modified base design using aoc, you can check with the link below in Chapter 2:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug-aocl-a10pciedk-platform.pdf

To renew Quartus license, you can follow the steps as link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/education/demonstrations/online/licensing/how-to-renew-an-expired-license.pdf

Thanks

Hi,

You can safely ignore that warning or delete that line and recompile. That line of code is the remnant of a port from older BSPs. There’s no need to call do_exit() function here. The compile warning occurs because the code is referencing the do_exit variable defined in one of the Linux kernel headers.

Thanks

Hi,

It looks like the driver compiles without any warnings or errors!

I have renewed our quartus license. However, when I try to compile the modified design, I get an error. I have tried to open the board.qsys and I get the same error there:

Error: DMA_system.fpga_to_sdram_dma.mm_read: mm_dma_read.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff)
Error: DMA_system.fpga_to_sdram_dma.mm_write: mm_dma_write.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff)
Error: qsys-generate failed with exit code 3: 2 Errors, 1 Warning
Error: DMA_system.fpga_to_sdram_dma.mm_read: mm_dma_read.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff)
Error: DMA_system.fpga_to_sdram_dma.mm_write: mm_dma_write.s0 (0x0..0x1fffffffff) is outside the master's address range (0x0..0xffffffff)
Error: qsys-generate failed with exit code 3: 2 Errors, 1 Warning

This happens when I:

1. Copy the example project 'vector_add'
2. cd into the project
3. cd into device/
4. Run the base compile: 'aoc -bsp-flow=base vector_add.cl'
5. cd vector_add/
6. copy the BSP from $INTELFPGAOCLSDKROOT/board/a10soc/hardware/a10soc_2ddr/* to .
7. open the project top.qpf in quartus
8. open the board.qsys file, which opens platform designer
9. Upgrade all the IPs to 19.1 or 19.3 (only some are 19.3)
10. Rename the 'Hard Processor System Intel Arria10 FPGA IP' from 'arria10_hps' to 'a10_hps'
11. Save
12. Run 'Sync System Infos'
13. Run 'Validate System Integrity'
14. Run 'Generate HDL'

Then I get the errors. Even though some of the HDL files are generated, Quartus fails to compile during the 'IP Generation' step