Forum Discussion
If anybody worked with Display Port on Arria 10 SX SoC or any other devkit, could you please share how to calculate/find PHY settings for the onboard DisplayPort? Or it is just an iterative process?
- VenT_Altera26 days ago
Frequent Contributor
Hi valentyns,
Thank you for your question. I will go through your enquiry and get back to you soon.
Thanks.
Best Regards,
Ven
- VenT_Altera25 days ago
Frequent Contributor
Hi valentyns,
The official Arria 10 design example is for the Arria 10 GX Dev Kit using the Bitec DP daughter card.
There is a design example for Arria 10 DP using the onboard connector for TX only, available in the FPGA Design Store. You may try out this design example. Please note that the Quartus version provided is 16.0.0, so you will need to perform an IP upgrade when migrating the design to QPDS Pro v25.1. Additionally, the design example targets the Arria 10 Dev Kit, so you will need to migrate it to the SoC board that you are using.
Thanks.
Best Regards,
Ven
- valentyns25 days ago
New Contributor
Hi Ven,
Thanks for your reply!
I have already tried to download that example, I successfully upgraded IP cores in Quartus Prime 18.1 Standard and synthesized design, but there is no software at all.
Do you have a full example for Arria 10 DP using the onboard connector for TX only?Best Regards,
Valentyns- VenT_Altera23 days ago
Frequent Contributor
Hi valentyns,
Thank you for the updates.
This is the only reference design available for Arria 10 onboard connector TX-only.
Thanks.
Best Regards,
Ven