New ContributorI want to transfer data from Nios (host) to a custom agent component on the FPGA through Avalon-MM interface. But, the host and agent operate at different clock speeds. How to facilitate data transfer in this scenario?
Super ContributorIn Platform Designer, just connect them together. The generated interconnect will automatically include CDC logic, either a FIFO or handshaking, depending on the options you set in PD (I think it's Interconnect Requirements in Standard and the Domains tab in Pro).
If you want more control, you can manually add/insert an Avalon clock crossing bridge from the IP Catalog.
New ContributorI am trying to use the Avalon-MM Clock Crossing Bridge, but am confused regarding a few connections on PD.
m0_clk and m0_reset are connected to the Nios processor clk and reset respectively (125 MHz) and s0_clk is connected to the clock bridge at 100 MHz. avalon_slave_0 is my custom Avalon-MM slave component. How should s0 and m0 interfaces be connected, if Nios is the host and avalon_slave_0 is the agent?
Super ContributorNios connects to s0, and m0 connects to your custom component.
Regular ContributorRegular ContributorHi
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards
Jingyang, Teh
