Nios to FPGA Avalon-MM

Question

I want to transfer data from Nios (host) to a custom agent component on the FPGA through Avalon-MM interface. But, the host and agent operate at different clock speeds. How to facilitate data transfer in this scenario?

sstrell · Answer

In Platform Designer, just connect them together. The generated interconnect will automatically include CDC logic, either a FIFO or handshaking, depending on the options you set in PD (I think it's Interconnect Requirements in Standard and the Domains tab in Pro).

If you want more control, you can manually add/insert an Avalon clock crossing bridge from the IP Catalog.

aamodini · Answer

I am trying to use the Avalon-MM Clock Crossing Bridge, but am confused regarding a few connections on PD.

m0_clk and m0_reset are connected to the Nios processor clk and reset respectively (125 MHz) and s0_clk is connected to the clock bridge at 100 MHz. avalon_slave_0 is my custom Avalon-MM slave component. How should s0 and m0 interfaces be connected, if Nios is the host and avalon_slave_0 is the agent?

sstrell · Answer

Nios connects to s0, and m0 connects to your custom component.https://www.intel.com/content/www/us/en/docs/programmable/683609/24-2/memory-mapped-clock-crossing-bridge-example.html

aamodini · Answer

Thank you.I get the following error when I connect m0 to custom componentError: system.mm_ccb_0.m0: avalon_slave_0.avalon_slave_0 (0x41160..0x4116f) is outside the master's address range (0x0..0x3f)I have assigned base addresses to all the components.

sstrell · Answer

You set the address width to only 4 bits for the bridge and you're using an address much larger than that.  Just turn on "Use automatically determined address width."

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Nios to FPGA Avalon-MM

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