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aamodini's avatar
aamodini
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2 years ago

Nios to FPGA Avalon-MM

I want to transfer data from Nios (host) to a custom agent component on the FPGA through Avalon-MM interface. But, the host and agent operate at different clock speeds. How to facilitate data transfe...
Fpga Devkit
aamodini's avatar
aamodini
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2 years ago

I am trying to use the Avalon-MM Clock Crossing Bridge, but am confused regarding a few connections on PD.

m0_clk and m0_reset are connected to the Nios processor clk and reset respectively (125 MHz) and s0_clk is connected to the clock bridge at 100 MHz. avalon_slave_0 is my custom Avalon-MM slave component. How should s0 and m0 interfaces be connected, if Nios is the host and avalon_slave_0 is the agent?

  • aamodini's avatar
    aamodini
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thank you.

    I get the following error when I connect m0 to custom component

    Error: system.mm_ccb_0.m0: avalon_slave_0.avalon_slave_0 (0x41160..0x4116f) is outside the master's address range (0x0..0x3f)

    I have assigned base addresses to all the components.

    • sstrell's avatar
      sstrell
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      You set the address width to only 4 bits for the bridge and you're using an address much larger than that. Just turn on "Use automatically determined address width."

      • aamodini's avatar
        aamodini
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        2 years ago

        I get other errors when I turn on "Use automatically-determined address width"