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Altera_Forum's avatar
Altera_Forum
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16 years ago

newbie help with WM8731 codec

Hi, I just got a cyclone ii dev kit and I'm having some problem with the audio codec on it.

I'm trying to make a dsp module which gets input from the line in, so I set up the codec for appropriate sampling frequencies and interface settings and all, and I just configured fpga to send the signal from the ADC right back to the DAC to see if it works, and connected my mp3 player to the line in terminal. But I got a lot of noise, although I can hear the music coming out. What do you think is the problem here?

regards,

Dongsu Lee

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You can use a scope or Signaltap probes to check the signals. It could be something as simple as a sign problem or a bit shift due to synchronization problems.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    but when I simulate it on quartus it works so perfectly.. I configured the codec for DSP mode with MSB available at the first negedge of the bclk.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    hello. I have to generate various tones (sounds) with the de2 carte.

    Can you help me please because it's for my studies and i don't know how to do.

    I have done the i2c communication. then i send a signal of 1khz frequency at the dacdat output but it doesnt function.

    I don't know really which adress and register to programm to function like i want (send a frequency to the input codec and have a sound at the speakers), which clock to programm and what value.

    thank you for your help
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    but when I simulate it on quartus it works so perfectly.. I configured the codec for DSP mode with MSB available at the first negedge of the bclk.

    --- Quote End ---

    i have experience too when using DSP module then i got noise on DAC . My problem is resolved by synchronizing DACLRCK (i'm using slave mode) , but in my case, i'm using i2s format bit .

    I think you should check again on Quartus, Do ADCLRCK clock have same phase with DACLRCK?

    I think you should synchronize it so DACLRCK have delay as many as latency clock on your DSP module