Occasional ContributorHi @Ana_R_Intel1 ,
I am trying out the I2C_RSU project in the below link using a Max 10 Development board. I understand this slave code will help in loading the 10M50 FPGA with a new image through I2C. Can we load the new image into FPGA using an Arduino i2c communication?
Can you provide test code or I2C commands used to test I2C_RSU.
https://community.intel.com/t5/FPGA-Wiki/Max-10-I2C-to-RSU/ta-p/735409
Regular ContributorHi,
IT is possible to use the Adruino I2C to send the data and update image. We do not have the example example I2C command. I would recommend you to follow the guideline on how to send the data and received data through I2C as below.
I2C Avalon 32 bit write - 10100110 follow by 4 byte Avalon address and 4 byte data.
I2C Avalon 32 bit read - 10101110 follow by 4 byte Avalon address.
Occasional ContributorHi,
Thanks for the quick reply. Basically from the test code I wanted to understand the below things
1. what will the slave address of FPGA with I2C_RSU code
2. When we write the image, into which CFM(0,1 or 2) will the image be written? Will it depend on the Avalon address that we write like in the slave if address starts with 0x10000, then image will be written to CFM1 etc.? Please correct me if I am wrong
3. And what speed the i2c should be configured?
Regards,
Ravi Kanth V
Regular ContributorHi Ravi,
1. what will the slave address of FPGA with I2C_RSU code
It will be "1010011".
2. When we write the image, into which CFM(0,1 or 2) will the image be written? Will it depend on the Avalon address that we write like in the slave if address starts with 0x10000, then image will be written to CFM1 etc.? Please correct me if I am wrong
Yes, you are correct. You need to refer back to your CFM addressing to determine the start of the specific CFM addressing.
3. And what speed the i2c should be configured?
It will depends on your I2C IP setting used.
Occasional ContributorHi,
I tried to scan the i2c slave address(of the Max10 device after loading I2C_RSU) using Arduino code and got the below result. I did not understand why I got so many addresses, which gave i2c acknowledge.
Then I am using the attached master_reader code to read data from the avalon address 0x0010_00F0, but I am reading back the address and not the data at that location.
Regular ContributorHi,
When you performed read, it will actually have address (1010xxx1) where the x is don't care bit.
Occasional ContributorHi,
I am able to read the data from any particular avalon address on the on-chip flash using the attached arduino code. But am not able to write anything. May be I have to unprotect the required sector in the control-registers (csr). I believe these are the 8 csr registers shown below(from the I2C_RSU example). Which of these are status and control registers. Correct me if my understanding is wrong or if I missed anything
Regards,
Ravi
Occasional ContributorHi,
In the I2C_RSU example, as I was mentioning earlier, I can see 8 control and status registers (0x20000 to 0x20007). Just to check I wrote into each of those registers and found that I could not write to registers(0x20000 to 0x20003) but could write to registers (0x20004 to 0x20007). This means one of registers from (0x20000 to 0x20003) is status register and one of the registers from (0x20004 to 0x20007) is control register. Can you help me identify the addresses of control and status registers.
Regular ContributorHi,
There is no setting for this as the FPGA should be able to handle the clk speed. If you are not confident then I would recommend you to implement the timing constraint to make sure it is meeting the highest frequency you are planning to used.
Occasional ContributorHi,
Can you also let me know, which are the correct addresses for control register and status register for on-chip flash?
Regards,
Ravi
Occasional ContributorHi,
I was able to perform RSU with I2C_RSU example through i2c interface of Arduino.
Thanks for the support. Now, I am trying to replace the I2C interface with SPI.
Can you let me know the SPI Avalon 32 bit write and read format, as you mentioned with I2C earlier.
Regards,
Ravi Kanth V
Regular ContributorHi,
Are you referring to Chapter 5 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf? If yes, then you need to follow Table 18.
