Forum Discussion
New ContributorAgilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)
Device: A5ED013BB32AE4SCS
Quartus Prime Pro 25.1.1 Build 125
I am trying to reconfigure a standalone fabric IOPLL at runtime using the EMIF Calibration IP (emif_io96b_cal), following the HSIO reconfiguration flow described in the Clocking and PLL User Guide (813671), section 6.1/6.4, and the approach discussed in this thread:
Agilex 5 reconfigurable PLL - emif | Altera Community - 122952
Setup:
- ps_pll: Intel IOPLL FPGA IP, "Enable dynamic reconfiguration of PLL using Calibration IP" = true, IOPLL Type = "I/O Bank" (only selectable value in the GUI), 50 MHz reference clock.
- EMIF Calibration IP (emif_io96b_cal), INSTANCE_ID = 0, NUM_CALBUS_PLLS = 1, NUM_CALBUS_PERIPHS = 0, AXI4-Lite subordinate port in FABRIC mode.
- pll_calbus / pll_calbus_readdata wired directly between the two IPs.
The Fitter fails during the very first placement/plan stage with:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)).
Error(175001): The Fitter cannot place 1 IOPLL, which is within IOPLL FPGA IP ps_pll_altera_iopll_2000_ihvozry.
Error(16234): No legal location could be found out of 11 considered location(s).
Error(175005): Could not find a location with: HVIO_IOPLL (6 locations affected)
Error(175008): Location was not in the legal region (5 locations affected)
I isolated this down to a minimal reproduction:
1) A plain, non-reconfigurable IOPLL alone: places fine.
2) The same IOPLL with calbus reconfiguration enabled, standalone (no EMIF IP at all): places fine.
3) The EMIF Calibration IP alone, calbus tied off, unconnected to any PLL: places fine.
4) The reconfigurable IOPLL and EMIF Calibration IP both present in the same design but NOT wired together (calbus tied off independently on each side): places fine.
5) The reconfigurable IOPLL wired to the EMIF Calibration IP via calbus (the actual intended configuration): fails with the error above, 100% reproducible, regardless of I/O pin location assignments (confirmed by removing every pin constraint from the design entirely - identical error, identical 6+5 location breakdown).
I have also tried, with no change to the error:
- Removing all pin location assignments (refclk, PLL outputs, etc.)
- Setting PLL_REFCLK_INPUT_TYPE to NOT_BALANCED on the IOPLL instance
- Quartus Interface Planner tool - "Update Plan" fails immediately with the identical underlying Fitter conflict, before it can even display a plan.
Can someone from Intel/Altera help me understand what is actually driving this placement conflict and how to resolve it? Happy to share the minimal reproduction project if useful.
Resolved -- and yes, the EMIF Calibration IP works perfectly for runtime IOPLL reconfiguration on Agilex 5. The problem was the PLL landing on an HVIO site instead of an HSIO one.
The key is in Error(175005): Could not find a location with: HVIO_IOPLL. The reconfigurable IOPLL + pll_calbus + EMIF Calibration IP flow requires the PLL to be placed on an HSIO IOPLL site. The Fitter was only finding HVIO PLL sites for it, and an HVIO PLL site cannot pair with the Calibration IP's hard block -- hence the placement conflict (14566 / 175001 / 16234).
ROOT CAUSE: whether the IOPLL is classified HSIO or HVIO follows from the bank of its reference-clock input pin, not from any IP parameter. In the minimal repro there are no pin constraints, so the Fitter is free to pick an HVIO PLL site for the refclk/PLL -- which then conflicts with the EMIF calbus connection. That is why steps 1-4 place fine and only step 5 (calbus actually wired) fails: it is the first point where the PLL is forced onto a site that must be HSIO, and nothing is steering it there.
FIX: constrain the PLL's reference clock to a pin in a bank that hosts HSIO-capable PLL sites. On the Terasic DE25-Standard, that is CLOCK2_50 = PIN_BM71 (bank 2A_T). The board's other 50 MHz oscillator, CLOCK0_50 = PIN_CH128 (bank 5A), is HVIO-only and reproduces this exact error, identical 6+5 location breakdown. So:
set_location_assignment PIN_BM71 -to <refclk> ;# HSIO-capable bank 2A_T
set_instance_assignment -name IO_STANDARD "1.2-V" -to <refclk>
With the refclk on the HSIO pin, the IOPLL places on an HSIO site, the pll_calbus / pll_calbus_readdata link to the EMIF Calibration IP is legal, the design fits, and runtime C-counter reconfiguration works -- I am using it for dynamic phase shift and getting clean, deterministic 39.06 ps steps on hardware.
ON THE EARLIER COMMENT ("HVIO reconfiguration is done by driving coreavl* directly; EMIF / pll_calbus not required"): that is consistent with this. There are two separate reconfiguration paths -- HVIO PLLs -> core_avl_* directly, and HSIO PLLs -> EMIF Calibration IP + pll_calbus. Error(175005): HVIO_IOPLL is precisely the symptom of trying to use the HSIO (EMIF) flow while the PLL is stuck on an HVIO site. The resolution is to make sure the PLL's bank matches the flow you want: to use the EMIF Calibration IP, put the reference clock on an HSIO bank.
Hope this helps anyone else hitting 175005 with the Calibration IP.
4 Replies
yoichiK_alteraContributor
Can you attach your small design which generate the fitter error ?
AdamAttached: pj_test_minimal_repro.zip - the minimal project that reproduces the error.
Extract to a short path (e.g. C:\pj_test\) to avoid Windows path-length issues with Quartus's generated files, then open test_pll.qpf and run a full compile.
test_pll_top.vhd instantiates just two IPs: pll.ip (Intel IOPLL FPGA IP, dynamic reconfiguration via Calibration IP enabled) and EMIF.ip (EMIF Calibration IP, standalone-PLL mode), connected only through the pll_calbus / pll_calbus_readdata signals. No pin assignments are present - the Fitter error happens purely from that calbus connection between the two IPs.
- yoichiK_altera
On Agilex 5, HVIO reconfiguration is performed by directly driving the PLL’s core_avl_* interface; EMIF Calibration IP and pll_calbus are not required.
- Adam
Resolved -- and yes, the EMIF Calibration IP works perfectly for runtime IOPLL reconfiguration on Agilex 5. The problem was the PLL landing on an HVIO site instead of an HSIO one.
The key is in Error(175005): Could not find a location with: HVIO_IOPLL. The reconfigurable IOPLL + pll_calbus + EMIF Calibration IP flow requires the PLL to be placed on an HSIO IOPLL site. The Fitter was only finding HVIO PLL sites for it, and an HVIO PLL site cannot pair with the Calibration IP's hard block -- hence the placement conflict (14566 / 175001 / 16234).
ROOT CAUSE: whether the IOPLL is classified HSIO or HVIO follows from the bank of its reference-clock input pin, not from any IP parameter. In the minimal repro there are no pin constraints, so the Fitter is free to pick an HVIO PLL site for the refclk/PLL -- which then conflicts with the EMIF calbus connection. That is why steps 1-4 place fine and only step 5 (calbus actually wired) fails: it is the first point where the PLL is forced onto a site that must be HSIO, and nothing is steering it there.
FIX: constrain the PLL's reference clock to a pin in a bank that hosts HSIO-capable PLL sites. On the Terasic DE25-Standard, that is CLOCK2_50 = PIN_BM71 (bank 2A_T). The board's other 50 MHz oscillator, CLOCK0_50 = PIN_CH128 (bank 5A), is HVIO-only and reproduces this exact error, identical 6+5 location breakdown. So:
set_location_assignment PIN_BM71 -to <refclk> ;# HSIO-capable bank 2A_T
set_instance_assignment -name IO_STANDARD "1.2-V" -to <refclk>
With the refclk on the HSIO pin, the IOPLL places on an HSIO site, the pll_calbus / pll_calbus_readdata link to the EMIF Calibration IP is legal, the design fits, and runtime C-counter reconfiguration works -- I am using it for dynamic phase shift and getting clean, deterministic 39.06 ps steps on hardware.
ON THE EARLIER COMMENT ("HVIO reconfiguration is done by driving coreavl* directly; EMIF / pll_calbus not required"): that is consistent with this. There are two separate reconfiguration paths -- HVIO PLLs -> core_avl_* directly, and HSIO PLLs -> EMIF Calibration IP + pll_calbus. Error(175005): HVIO_IOPLL is precisely the symptom of trying to use the HSIO (EMIF) flow while the PLL is stuck on an HVIO site. The resolution is to make sure the PLL's bank matches the flow you want: to use the EMIF Calibration IP, put the reference clock on an HSIO bank.
Hope this helps anyone else hitting 175005 with the Calibration IP.
