Forum Discussion
5 Replies
- Pooja_03
New Contributor
Hi,
Gentle reminder!
Thank you
- FvM
Super Contributor
Hi,
MAX10 VCCIO bank 1 and 8 are monitored by POR circuit and prevent device configuration if not powered.
Other VCCIO bank supplies are not monitored. MAX10 datasheet specifies however:
"VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities."
Obviously this doesn't answer your question "what will happen if". My guess is that it won't damage the FPGA. Ramping VCCIO within legal VCCIO levels (1.2 to 3.3 V) should be also possible as long as maximum pin currents are observed. - AqidAyman_Altera
Regular Contributor
Hello,
I wish to follow up with you, since the reply provided, do you need more support or clarification on this question before I close this thread?
Regards.
Aqid
- Pooja_03
New Contributor
Hi Aqid,
Thank you for your response.
It is cleared. You may close this thread.
Thank you
- AqidAyman_Altera
Regular Contributor
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.