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sakthi_iitm's avatar
sakthi_iitm
Icon for New Contributor rankNew Contributor
4 years ago

MAX10 ADC Sequencer problem

I am using MAX10 internal ADC with Channel 1 and Channel 2. In the platform designer I have invoked ADC control core only (Soft IP) and now I want to change the ADC command channel ( Between channel 1 and channel 2 ) and separate the ADC response data separately and store in different registers for the both the channels.

Can I please get example ( VHDL code) for using ADC control core only to extract the two ADC response datas separately and store in different registers?

1 Reply

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    You can generate ADC IP with sequencer logic which adds additional blocks to the control only core. Other option is to check for an example design on Intel FPGA design store: FPGA Design Store | Intel


    Regards