Occasional ContributorI'm trying on arria 10 SoC GHRD and like to add a register block on FPGA side to LW AXI4 interface for control and status.
There is hps_lw_axi_master connected to SYS ID, PIO etc.
How would my fpga register-block connected to this interface. Thanks.
Super ContributorAre you asking how to create a custom component and connect it to the lightweight bridge? The Platform Designer user guide discusses this and this training goes into detail on the process:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html
#iwork4intel
Regular ContributorHi,
Here are some useful guide and documentation on the LW bridge for your reference:
https://www.youtube.com/watch?v=RTmDgNXIwKQ
Occasional ContributorHi, it's fine now. Thanks.
