Forum Discussion
User1580871742356367
Occasional Contributor
Occasional Contributorlwh2f
I'm trying on arria 10 SoC GHRD and like to add a register block on FPGA side to LW AXI4 interface for control and status.
There is hps_lw_axi_master connected to SYS ID, PIO etc.
How would my ...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Here are some useful guide and documentation on the LW bridge for your reference:
https://www.youtube.com/watch?v=RTmDgNXIwKQ
User1580871742356367Hi, it's fine now. Thanks.
