Forum Discussion

SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Looping back a clock to its source

Hello,

Port 'X' is an FPGA clock pin.

It's defined using a "create_clock" SDC command.

I have a requirement to drive this clock to an input port 'Y' like this:

Y <= X ;

I want the delay between X and Y to be as little as possible.

What constraint do you advice to use ?

4 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    May I know what is Y? Is it a clock pin for core register or clock pin for some IP?

    Thanks.

    Best regards,

    KhaiY

  • SKon1's avatar
    SKon1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Y is an FPGA pin that sends the clock (X) to another ASIC.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    You cannot control the clock delay using SDC constraints. You may use different clock structure for your design. This includes global clock networks, regional clock networks, fast regional clock networks, and periphery clock networks. In general, fast regional clocks have less delay to I/O elements than regional and global clocks, and are used for high fan-out control signals. Regional clocks provide the lowest clock delay and skew for logic contained in a single quadrant. Placing clocks on these low-skew and low-delay clock nets provides better tCO performance.

    Thanks.

    Best regards,

    KhaiY