Forum Discussion
SKon1
Occasional Contributor
Occasional ContributorLooping back a clock to its source
Hello, Port 'X' is an FPGA clock pin. It's defined using a "create_clock" SDC command. I have a requirement to drive this clock to an input port 'Y' like this: Y <= X ; I want the delay between ...
SKon1Occasional Contributor
Occasional ContributorY is an FPGA pin that sends the clock (X) to another ASIC.
