Issue with HPS Reset Not Responding in Agilex 7 (AGFB014R24B) Powered via MAX 10 CPLD

Hi all,

I am currently working with the Agilex 7 series FPGA, part number AGFB014R24B, which is powered up through a MAX 10 CPLD IC via power sequencing.

The MAX 10 CPLD is responsible for enabling the voltage regulators and powering up the main power supply for the Agilex 7 FPGA. I have followed the power-up sequencing order as recommended by Intel, and also referred to two development kits that use the same Agilex 7 FPGA and MAX 10 CPLD-based power-up mechanism.

All voltage regulators were verified to be providing the correct outputs before proceeding.

After successfully powering up the Agilex 7 device using the MAX 10 CPLD, I observed in the Configuration Debugger → Device Info that the HPS reset signal is not responding—it is neither high nor low.

Below are the current configuration pin assignments from the tool settings:

1. PWRMGT_SCL → SDM_IO0

2. PWRMGT_SDA → SDM_IO12

3. CONFIG_DONE → SDM_IO16

4. HPS_COLD_nRESET → SDM_IO13

5. Configuration Clock Source → 125 MHz

Could anyone please advise if this configuration is correct and what might cause the HPS_COLD_nRESET signal to not toggle or respond?

Thanks in advance.