New Contributor
Frequent ContributorHi,
These are the few documents that I found, not sure whether you already have the manual documentation and design as they have the design for reading the ADC and also triggering the LEDs
For ADC usage and implementation, you can refer to the Terasic DE1 SOC manual page 83 and example design provided by Terasic
Manual:
Design files for the demo (select ref F):
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836&PartNo=4
Document on ADC (its based on Quartus 18 but still applicable)
Thanks
Regards
Kian
New ContributorWell, I genuinely admire the time you've invested in. But the issue I encountered was bit different. Though the test bench generated the exact timing diagram that was required to program an ADC. But when I used the Signal Tap analyzer, it happened to me that the latch of logic 1 was generated at the ADC_DIN pin due to which channel 07 of ADC was selected at the start of each conversion. The difference between test bench and Signal Tap Analyzer behaviour was quite surprising for me. When I modified the code a bit, the Correct channel of ADC has been configured.
Thank You.
Frequent ContributorHi,
Sorry for the delay in replying, was in a 3 day offsite training. Glad that your code is working now, as for your question on the Testbench simulator, I was discussing with my colleague here on this case and we suspect that you might need to add in latency manually to simulate close to real work situation even though the simulated waveform is matching to the one specified in the guide. I wonder whether Terasic would have more information on this since they build the custom DE 1 SOC board.
Thanks
Regards
Kian
