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himanshuvaria's avatar
himanshuvaria
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Is it possible to run NIOSV through SDRAM ?

Hello, I am developing a project where NIOS II needs to replaced with NIOSV processor. When my design was having NIOS II as CPU, I was running the software code through External SDRAM on the Cyclon...
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himanshuvaria's avatar
himanshuvaria
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

I want to inform you that the link you provided has already been working for me. But it's when On-Chip-Ram has been used for the reset vector of NIOSV. I am using SDRAM Controller IP to program the external SDRAM as program memory. I have set the reset vector to sdram_controller_ip in the QSYS system and have made connections based on that.

When I am using On-Chip-Ram as program memory, then there is no issue, everything works as expected. But when I use external SDRAM as program memory, then I am able to run the ELF on the board but the NIOSV code does not executed. The reason to use external SDRAM is that my Cyclone IV E(EP4CE40F23C8) does not have enough M9K blocks to fit the design due to which I have to use external SDRAM.

My question to you is that can I use external SDRAM as program memory for running NIOSV processor. Please consider the following devices that I am using for you reference.

  1. FPGA used : Cyclone IV E (EP4CE40F23C8)
  2. External SDRAM Part No : W9816G6IH ( WinBond )

Below is the image of my QSYS system configuration.

The reset vector is set as below:

Please let me know if I am missing something in the hardware design.

Thanks in advance.

Regards,

Himanshu