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himanshuvaria's avatar
himanshuvaria
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Is it possible to run NIOSV through SDRAM ?

Hello,

I am developing a project where NIOS II needs to replaced with NIOSV processor. When my design was having NIOS II as CPU, I was running the software code through External SDRAM on the Cyclone IV E Kit(EP4CE40F23C8). It's working fine with NIOS II. Able to run the software program.

Now, when I replaced the NIOS II processor with the NIOSV processor, I am not getting the expected results. I am trying to print a Simple "Hello World" code through the NIOSV processor with the same configuration of design. Almost all BSP settings are same for NIOSV processor as of the NIOS II. Still not getting the results.

I want to inquire that if we can run the NIOSV processor through external SDRAM or not ?

Please note that I am not talking here about booting the NIOSV. I am simply running the software image through RiscFree IDE software on the external SDRAM of the board.

Regards,

Himanshu

Fpga Devkit

11 Replies

    • himanshuvaria's avatar
      himanshuvaria
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hello,

      I want to inform you that the link you provided has already been working for me. But it's when On-Chip-Ram has been used for the reset vector of NIOSV. I am using SDRAM Controller IP to program the external SDRAM as program memory. I have set the reset vector to sdram_controller_ip in the QSYS system and have made connections based on that.

      When I am using On-Chip-Ram as program memory, then there is no issue, everything works as expected. But when I use external SDRAM as program memory, then I am able to run the ELF on the board but the NIOSV code does not executed. The reason to use external SDRAM is that my Cyclone IV E(EP4CE40F23C8) does not have enough M9K blocks to fit the design due to which I have to use external SDRAM.

      My question to you is that can I use external SDRAM as program memory for running NIOSV processor. Please consider the following devices that I am using for you reference.

      1. FPGA used : Cyclone IV E (EP4CE40F23C8)
      2. External SDRAM Part No : W9816G6IH ( WinBond )

      Below is the image of my QSYS system configuration.

      The reset vector is set as below:

      Please let me know if I am missing something in the hardware design.

      Thanks in advance.

      Regards,

      Himanshu

    • himanshuvaria's avatar
      himanshuvaria
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hello,

      I would be waiting for your feedback.

      Thanks in advance !!

      Regards,

      Himanshu

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    I got your questions now, I will need to check again on the limitations for your request and device, I will get back to you as soon as possible, I might come back to get some further details.


    • himanshuvaria's avatar
      himanshuvaria
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi,

      Thanks for looking out. I would be waiting for your response.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Is this the same issue as the one with your 16-bit data bus to your Nios V?


    • himanshuvaria's avatar
      himanshuvaria
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi,

      Yes, it is the same issue as of the 16-bit data bus to the NIOSV. If we keep aside the SDRAM, and try to use On-Chip-Ram as program memory, where the data width of On-Chip-Ram IP is set to 16 bits, then same issue arises when running the ELF. The ELF gets downloaded successfully but the Debugger Console shows warning : "Cannot access memory at address 0x29c". When the data width of On-Chip-Ram IP is set to 32 bits everything works fine as expected.

      With NIOS II, we were capable to configure the device with 16-bits On-Chip-Ram, but NIOSV does not seems to work like that. So I think due the data width of SDRAM being 16-Bits set in the QSYS system, similar issues are occuring in that cases. Any help regarding to solve this would be appreciated.

      Thanks !!!!

      Regards,

      Himanshu

      • himanshuvaria's avatar
        himanshuvaria
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        Hi,

        Any update on the regarding the issue ? Please share your response !!

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.