New ContributorObjective: Synthesize Triple Speed Ethernet IP variant (with MAC and 1000 Base - X) in my Cyclone IV GX transceiver kit. I'd like to then connect an Ethernet cable to my FPGA and then observe the RX signals toggle (sop,eop,data_valid,data)
I have the generated TripleSpeedEthernet.v file. How the hell do I assign IO for this design? I'm confused.
ContributorHie,
To understand how to assign IO, you can refer to the Reference or Example Design. Generating an example design for TSE IP is covered in our documentation below (Refer to Pg 18 to links to document related to generating reference design for different devices):
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
Please let me know if the above document helps you resolve your issue.
Regards,
Nathan
New ContributorContributorSure do let me know if you have further questions.
