Hi Jingyang,
Thank you for your feedback.
I have not had a chance to try the GSRD yet. I am willing to give the GSRD an attempt if that is what you advise. However, I am in the U.S., working remotely the first part of the week and we have holiday events later this week. I likely won't be able to provide a further update until I am back in the office and able to test the GSRD - I expect this to be 11/27.
I have also contacted my Intel account technical representative who is working on getting an IPS ticket setup for this issue. He is aware we have been working this issue, you may be contacted internally.
Regards,
Brandon
P.S. - For completeness, attaching the DIP switch settings being used on my board:
DIP switch settings for PCIe P-tile DK:
Legend:
O => OPEN
C => CLOSED
x => DON'T CARE
######### STANDALONE CONIFGURATION ###########
SW1 (MSEL)
OOOx : JTAG programming mode only
SW2
OOOO : USB JTAG Enabled, Si5341 enabled, PCIe on-board ref clock enabled, UART enabled
SW3
OOOO : Enable all PMBUS and I2C slaves
SW4 (JTAG chain selects)
OOCO : UBII JTAG enabled (no PCIe JTAG), Bypass MICTOR JTAG (HPS), ENABLE FPGA, ENABLE MAX10 in JTAG CHAIN
SW5 (Power switch)
x : ON/OFF
SW6 (PCIe configuration)
COOO : Set for PCIe x16 mode
SW7
C : Select PCIe ref clock from Si clock IC
##############################################
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