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BChiw's avatar
BChiw
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7 years ago

Intel EMIF FPGA IP DTS / DTB error.

Hello,

Need help for this DTS/DTB generation error.

We are using this link as the base design:

https://rocketboards.org/foswiki/Projects/A10AVCVPCIeRootPortWithMSI

Then we added the FPGA DDR4 interface, "emif_0". We are having this DTS/DTB generation errors:

> sopc2dts -v -v --input ghrd_10as066n2.sopcinfo --output ghrd_10as066n2.dts --board hps_a10_common_board_info.xml --board ghrd_10as066n2_board_info.xml --bridge-removal all --clocks

Component emif_0 of class altera_emif is unknown

Component emif_0_arch of class altera_emif_arch_nf is unknown

Component emif_0_ecc_core of class altera_emif_ecc is unknown

Component emif_0_col_if of class altera_ip_col_if is unknown

Component emif_0_col_if_colmaster of class alt_mem_if_jtag_master is unknown

Component emif_0_cal_slave_component of class altera_emif_cal_slave_nf is unknown

> dtc -I dts -O dtb -o ghrd_10as066n2.dtb ghrd_10as066n2.dts

ERROR (phandle_references): Reference to non-existent node or label "emif_0_arch"

ERROR: Input tree has errors, aborting (use -f to force output)

Internet search showed instructions for custom IP, but error is from Intel EMIF IP.

Attaching the files that may be needed to check:

ghrd_10as066n2.qsys

subsys_pcie.qsys

ghrd_10as066n2.sopcinfo

ghrd_10as066n2.dts

dts_error.txt // error message log of sopc2dts and dtc commands

Thanks,

--barny

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  • BChiw's avatar
    BChiw
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hello,

    Thank you for the suggestion, tried it below:

    // emif_0_ecc_core: unknown@0x100000040 {

    // compatible = "unknown,unknown-16.1";

    // reg = <0x00000001 0x00000040 0x40000000>;

    // clocks = <&emif_0_arch 0>;

    // }; //end unknown@0x100000040 (emif_0_ecc_core)

    memory {

    device_type = "memory";

    reg = <0xc0000000 0x20000000>;

    }; //end memory

    It produced a warining:

    >dtc -I dts -O dtb -o trial_20190325a.dtb ghrd_10as066n2_20190325.dts

    Warning (reg_format): "reg" property in /sopc@0/bridge@0xc0000000/memory has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)

    Did somed edit (copied other entry under sopc@0):

    memory {

    device_type = "memory";

    reg = <0x00000001 0xc0000000 0x20000000>;

    }; //end memory

    >dtc -I dts -O dtb -o trial_20190325a.dtb ghrd_10as066n2_20190325.dts

    No more warning/error messages. Will try this in actual FPGA kit once project resources are returned.

    Thank you very much for the help.