Informations about DUAL XAUI TO SFP+ HSMC BOARD/BCM8727

Hello

Excuse my English in advance.

I'm also using DE4 and DUAL XAUI TO SFP+ HSMC board, and have almost the same problem as you have. Unfortunately DUAL XAUI TO SFP+ HSMC board datasheet I've received from Altera, don't contain any information about BCM8727 and its registers. But, I've found list of MDIO registers in DP83848VYB datasheet. Maybe it will help you. And could you please tell me, what are these "magic number" that you send over MDIO interface?

Don't worry, my English isn't perfect either;)

I send the following data over MDIO2(i don't know, why it doesn't work with MDIO1, but the port is addressed via bits 12 down to 8 of Address - you can find the details in the 'Embedded Peripherals IP User Guide' on p. 140):

Address, Data

x"81000104", x"0000C8E4"

x"81010104", x"000080E4"

x"81000004", x"0000C8E4"

x"81010004", x"000080E4"

Basically this is the flip_lanes command from the demo design tcl-skripts(http://www.altera.com/support/refdesigns/ip/interface/ref-10gbe-hardware-demo.html).

And thx for the hint with the DP83848VYB, I will take a look on it.

Hi,

Were you guys able to solve the problem? I'm also seeing a similar issue.

Thanks

Hello,

Are you using multiple SFP+ interfaces?

I have a Stratix V GX Development Board and I've successfully used one SFP+ interface on channel 2. When I try to instantiate two 10 GbE Design Example modules on qsys and connect each of them to separate xaui channels, quartus give me this fitter error:

-Error (175001): Could not place auto-promoted clock driver

--Info (175028): The auto-promoted clock driver name: EthExampleQsys:ETH_EXAMPLE_QSYS|EthExampleQsys_eth_10g:eth_10g_1|altera_xcvr_xaui:xaui|sv_xcvr_xaui:alt_xaui_phy|sv_xcvr_low_latency_phy_nr:alt_pma_0|sv_xcvr_custom_native:sv_xcvr_custom_inst|sv_xcvr_native:gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pld_pcs_interface_rbc:inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0

--Info (11237): Already placed at this location: auto-promoted clock driver EthExampleQsys:ETH_EXAMPLE_QSYS|EthExampleQsys_eth_10g:eth_10g|altera_xcvr_xaui:xaui|sv_xcvr_xaui:alt_xaui_phy|sv_xcvr_low_latency_phy_nr:alt_pma_0|sv_xcvr_custom_native:sv_xcvr_custom_inst|sv_xcvr_native:gen.sv_xcvr_native_insts[0].gen_bonded_group.sv_xcvr_native_inst|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pld_pcs_interface_rbc:inst_sv_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0

Does anyone have any clue of what may be this error?

Thanks!

Oh, I'm using the same REFCLK for both xcvr's, since there is no other REF_CLK for XAUI interfaces on this board.

About those magic numbers for lane swapping, I've realized that they're must not be used if you are not making a loopback, so using a SFP+ on channel 1 probably doesn't need any configuration if you are connecting it to another SFP+ interface.

Those BCM8727's registers are difficult to find because Broadcom doesn't distribute their datasheets publicly (you must have an special account to access their system), and Terasic is not quite "user-friendly" in terms of documentation and support.

--- Quote Start ---

Hello,

I have a Stratix V GX Development Board and I've successfully used one SFP+ interface on channel 2.

--- Quote End ---

Slightly diverting the conversation here...

I have a Stratix V GS (Stratix V DSP) development kit and the Terrasic Dual XAUI TO SFP+ development kit. The example project provided by Altera for 10Gbe uses the Statix IV development kit and a custom QSYS component which combines the 10Gbe MAC and the XUAI.

Please could you briefly outline the steps you had to take to build the MAC and PHY for your Stratix V. For example, did you use the example custom QSYS component and modify it or did you just grab all the bits and pull them together yourself?

If the answer is the latter I will have more questions :)

Thanks!