If there is a delay on the clock, will it affect LVDS reception?

hi

any of the PLL outputs through a global buffer (BUFG), and the ... LVDS Clock P ... complement signals are fed through master and slave input delays (both ... reception of data but does affect the current position of the sample ..

Hi,

Are you refereing to internal buffer or external buffer to FPGA

Hi ,

In cyclone IV there is buffer .

Hi ,

Kindly let me know if you need further assistance

Hi Rahuls，

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No more questions, Thanks

Ted

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Hi ,

Really glad to know .

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