TGao
Occasional Contributor
Occasional ContributorIf there is a delay on the clock, will it affect LVDS reception?
Hi We're going to add a buffer to the clock pair on the circuit，I'm not sure if it can affect the lvds reception? Ted.Gao
Forum Discussion
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
Are you refereing to internal buffer or external buffer to FPGA
TGaoOccasional Contributor
Occasional ContributorHi EahulS,
There are no internal buffer in CIV, and no external buffer.
