Forum Discussion

TGao's avatar
TGao
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

If there is a delay on the clock, will it affect LVDS reception?

Hi ​ We're going to add a buffer to the clock pair on the circuit，I'm not sure if it can affect the lvds reception? Ted.Gao
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

Are you refereing to internal buffer or external buffer to FPGA

  • TGao's avatar
    TGao
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago
    Hi EahulS, There are no internal buffer in CIV, and no external buffer.