HPS access the Avalon Memory-Mapped whether in pending status

I use Avalon Memory-Mapped (Avalon-MM) interfaces to implement read and
write interfaces for master and slave components. HPS side is master and FPGA side is slave.

I find that HPS software code could not be pending when HPS launch one write/read transmission in waitrequest mode(the Avalon slave asserts waitrequest signal).

In the document description, " A slave asserts waitrequest when unable to respond to a
read or write request. Forces the master to wait until the interconnect is ready to proceed with the transfer. At the start of all transfers, a master initiates the transfer and waits until waitrequest is deasserted." My question is how about the HPS write/read MM software code, whether also be pending like the Avalon master, how about that scheme need to be configured if we want to pend software code runs on ARM?