Forum Discussion
how to use get_device_names
hi.I have some problems in FPGA . Now i am debugging my application using VJTAG. but I cannot get the device name using get_device_names'
The command is exec C:\\altera\\10.0\\quartus\\bin64\\quartus_stp --tcl_eval get_device_names -hardware_name USB-Blaster[usb-0]
some errors happen. In the attachment you will see it.how I solve it?the quartus II version is 10. FPGA EP3C25Q240
33 Replies
- KhaiChein_Y_Intel
Regular Contributor
Hi,
May I know if you have any updates?
Thanks.
- CKang11
New Contributor
hi, the question is solved. the command must run in the xterm. i want to know if virtual jtag and signal tapII can run for debug in one project at the same time ? I try running vjtag and signal tap II at the same time ,but the signal tap II can not be trigered .why? Is it because they share one jtag interface , which make them not be used at the same time?
- KhaiChein_Y_Intel
Regular Contributor
Hi,
Do you see any error message?
Thanks.
- CKang11
New Contributor
there is not any error messege. only not triggered . - CKang11
New Contributor
could the command device _lock lead to it? According to the manual , device_lock Description Obtain an exclusive JTAG communication to the devicefor the subsequent IR and DR shift operations. The device must be locked before any instruction and/or data register shift operation. This should be used as little time as possible as it denies the access of other applications to this chain. The command, unlock, should be called as soon as possibleto allow other applications to access the device.
- KhaiChein_Y_Intel
Regular Contributor
Hi,
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf (Page 6), you can use the Virtual JTAG IP core in tandem with other on-chip debugging applications, such as the Signal Tap logic analyzer, to increase debugging visibility.
Thanks.