How to fully control the Avalon MM bridge by HPS baremetal?

Question

Hi,I'm using CycloneVsoc baremetal HPS with FPGA.I have multi channel from HPS to FPGA, they are using H2F bridge or LWH2F bridge(AXI bridge) through AvalonMM bridge.I've read the Avalon Bridge UG and noticed the Avalon MM bridge has a lot of other signals such as valid,ready,allow,burst_count,etc.It is symple to manage these signals in FPGA module,But I didn't find any control method through HPS. Now what I know is that using alt_write_xxxx() and alt_read_xxxx() to set write and read / writedata and readdata signals, as for other signals, I don't know how to set.Could you please give me a guide?Thank you.ReguardsAlex

sstrell · Answer

All other signals are part of the Avalon interface standard.  You shouldn't need to manage them when you are writing code, even at the baremetal level.

calex · Answer

Hi,Thank you for the reply,I still dont quite understand why, for example:if I want to use byteenable to point which byte is useful, as a HPS master , how should I write the codes from HPS side?The other example maybe:if I want to use burst transfer for H2F bridge,How should I use burst transfer from the HPS side(could you show me the baremetal C codes to do so?translate 128 bit for example.)?The other problem is data width of H2F bridge, the H2F bridge could be 128 bit wide, but L2 interconnection ,according to the HPS RM, is 64 bit wide, then is any width above 64 bit meaningless?Thank you again.Best ReguardsAlex

sstrell · Answer

Many options are set when you specify parameters settings for the HPS IP which then get integrated into the first-stage bootloader. That is where all the hardware options are set. If you're a software/baremetal developer, that's at a higher level of development, making use of the HWLibs and the baremetal commands documented as part of HWLibs to perform operations with the HPS in software including things like accessing data at certain address locations and then choosing what data or what bytes you need. You should take a closer look at HWLibs to find out how to do things you are referring to.

As for the H2F bridge width, yes, you can set the bridge itself to 128 bits on the FPGA side and it is fixed at 64 bits on the HPS side. You can still access 128 bit agents in the FPGA (if you have any). It will just require two cycles for the processor to access the full 128 bits.

calex · Answer

Hithank you for your fast reply,Now I get your point,but HWlib didn't provide any translation longer than 64 bits.My goal is to translate 128 bit-long data as fast as possible, which I want to use burst tranfer.As my understanding, 128 bit burst is faster than two 64 bit tranfers.Now I just dont know how to achieve my goals by C on the HPS side.Bset ReguardsAlex

aikeu · Answer

Hi CAlex,There is a msgdma design example which may help for understanding, can check the application c code under the software folder on the project file:https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335More information regarding the MSGDMA is from the embedded peripheral user guide:https://www.intel.com/content/www/us/en/docs/programmable/683130/21-2/introduction.htmlThanks.Regards,Aik Eu

Forum Discussion

How to fully control the Avalon MM bridge by HPS baremetal?

6 Replies

Recent Discussions

Stratix 10 Development Kit HiLo connector

Regarding Quartus Prime License Activation for the Agilex 5 Evaluation Kit

DE1-SoC project compiles, but board programming fails 42%. Other programs work fine

Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue

DE10-Lite unable to flash?