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CAlex's avatar
CAlex
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2 years ago

How to fully control the Avalon MM bridge by HPS baremetal?

Hi, I'm using CycloneVsoc baremetal HPS with FPGA. I have multi channel from HPS to FPGA, they are using H2F bridge or LWH2F bridge(AXI bridge) through AvalonMM bridge. I've read the Avalon Bridge...
Fpga Devkit
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

All other signals are part of the Avalon interface standard. You shouldn't need to manage them when you are writing code, even at the baremetal level.

CAlex's avatar
CAlex
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2 years ago

Hi,

Thank you for the reply,

I still dont quite understand why,

for example:

if I want to use byteenable to point which byte is useful, as a HPS master , how should I write the codes from HPS side?

The other example maybe:

if I want to use burst transfer for H2F bridge,

How should I use burst transfer from the HPS side(could you show me the baremetal C codes to do so?translate 128 bit for example.)?

The other problem is data width of H2F bridge, the H2F bridge could be 128 bit wide, but L2 interconnection ,according to the HPS RM, is 64 bit wide, then is any width above 64 bit meaningless?

Thank you again.

Best Reguards

Alex

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Many options are set when you specify parameters settings for the HPS IP which then get integrated into the first-stage bootloader. That is where all the hardware options are set. If you're a software/baremetal developer, that's at a higher level of development, making use of the HWLibs and the baremetal commands documented as part of HWLibs to perform operations with the HPS in software including things like accessing data at certain address locations and then choosing what data or what bytes you need. You should take a closer look at HWLibs to find out how to do things you are referring to.

    As for the H2F bridge width, yes, you can set the bridge itself to 128 bits on the FPGA side and it is fixed at 64 bits on the HPS side. You can still access 128 bit agents in the FPGA (if you have any). It will just require two cycles for the processor to access the full 128 bits.

    • CAlex's avatar
      CAlex
      Icon for Contributor rankContributor
      2 years ago

      Hi

      thank you for your fast reply,

      Now I get your point,

      but HWlib didn't provide any translation longer than 64 bits.

      My goal is to translate 128 bit-long data as fast as possible, which I want to use burst tranfer.

      As my understanding, 128 bit burst is faster than two 64 bit tranfers.

      Now I just dont know how to achieve my goals by C on the HPS side.

      Bset Reguards

      Alex