"How to connect between Cyclone@10[10CX150] and AS4C32M16D3[DDR3] "?, and How to know the PIN map of Cyclone@10 for DDR3 in detail ?
I am using Cyclone@10 to design my project, i wanna use the interface of DDR3(hard memory controller), the DDR3 is AS4C32M16D3-12BCN,
but My question is "How to connect between Cyclone@10 and AS4C32M16D3 "?, and How to know the PIN map of Cyclone@10 for DDR3 in detail ? I have looked for many spec, but No result...
Memory is connected to the FPGA by memory controller and interfaces which is implemented on the FPGA by using software (Quartus) called Memory Interface.
You need to connect DDR pins to the dedicated pins on the FPGA and use appropriate power supply for power pins of the FPGA. Then you can use DDR controller IP in your FPGA design. This is the flow on how to design the External Memory Interface (EMIF) IP.
Regarding the pin connection, I attached together the External Memory Interface Pin information for Cyclone 10 GX and Pin information for Cyclone 10 GX for your reference. Or you can directly select the pin-out files based on the device you are using in this link --> https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Yes it is fixed location in an I/O bank and you cannot change it.
As you see in the EMIF Pin Information that I attached before, for Cyclone 10 GX (all packages), the add/cmd pin is predefined in Index 12-30 (highlighted in yellow).
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