"How to connect between Cyclone@10[10CX150] and AS4C32M16D3[DDR3] "?, and How to know the PIN map of Cyclone@10 for DDR3 in detail ?

Hi Sir,

Memory is connected to the FPGA by memory controller and interfaces which is implemented on the FPGA by using software (Quartus) called Memory Interface.

You need to connect DDR pins to the dedicated pins on the FPGA and use appropriate power supply for power pins of the FPGA. Then you can use DDR controller IP in your FPGA design. This is the flow on how to design the External Memory Interface (EMIF) IP.

For more details, you can refer to this EMIF handbook for more details --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf

Also, here is tutorial on how to create design example for External Memory Interfaces Intel Cyclone 10 GX FPGA IP--> https://www.intel.com/content/www/us/en/programmable/documentation/ipw1503410337586.html

Regarding the pin connection, I attached together the External Memory Interface Pin information for Cyclone 10 GX and Pin information for Cyclone 10 GX for your reference. Or you can directly select the pin-out files based on the device you are using in this link --> https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

For the pin connection guideline you can refer to this handbook --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf

Hope this is helpful for you.

Thanks

Regards,

NAli1