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ChiNguyen18's avatar
ChiNguyen18
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1 year ago
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How to Configure Nios II (PFGA Side) to Execute Code from SDRAM (HPS Side) on DE10-Nano

Hello everyone, I’ve been working with the DE10-Nano board, following the guide provided in this link: SocBootFromFPGA (https://community.intel.com/t5/FPGA-Wiki/SocBootFromFPGA/ta-p/735773). I succ...
Fpga Devkit
  • tehjingy_Altera's avatar
    tehjingy_Altera
    1 year ago

    Hi


    In your use case, the HPS is using the DDR, the Nios could not run from the DDR.

    The Nios would need a dedicated DDR to run on.



    Regards

    Jingyang, Teh


ChiNguyen18's avatar
ChiNguyen18
Icon for New Contributor rankNew Contributor
1 year ago

Thank you.

I tried adding a DDR3 SDRAM controller with UniPHY in Qsys, but I received an error: "illegal connection on io input buffer primitive soc_system". It appears that the DDR3 is already connected to the controller on the HPS side, and the FPGA cannot directly connect to the DDR3 without using the F2H bridge.

From what I understand, since the DDR3 is managed by the HPS, Nios II on the FPGA side must access it via the F2H bridge. However, I’m unsure about how exactly Nios II can fetch instructions from DDR3 through the F2H bridge and whether a memory span extender is required in this case.