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RBens's avatar
RBens
Icon for New Contributor rankNew Contributor
7 years ago

How do I restore/reset Arria 10 SoC FPGA development boards that are not accessible via JTAG anymore?

I work for Intel and am submitting this case on my customers behalf. I do not have physical possession of the board and need a contact that my customers can send the boards to for repair.

Regards,

Ron

Customer Issue details below:

S/N : 10ASXSoC002850

P/N: 6XX-44382R-0M (I copy these here as the tool was not able to find my product)

Dear Sir/Madam,

I request support to restore/reset two Arria 10 SoC FPGA development boards. These are not accessible via JTAG anymore. My software is Quartus 17.1

I use JTAG server to program these boards. I have used JTAG server programming for a while now without problems, on other boards too. The project that I was testing at that time included signal tap; this may or may not be related. In previous tests, the signal tap communication was behaving strangely, as I could not have a signaltap session that would last for more than a few seconds.

After the programming, the red LED D17 blinks at approx 1 second intervals. I cannot access the FPGA nor I/O Max V on the JTAG chain. This happened for two different boards on different days.

The on-board byte blaster seems to be working. At least the Quartus programmer says it's detected. I returned all dipswtiches and jumpers to the default position, but the JTAG is still undetected.

I think the simplest solution is to send the boards somewhere to Altera/Intel and get them reflashed/restored/reset. Would save both sides some time and energy, since we've been going at this for almost a month now.

Thanks!

Francisco

4 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi RBens,

    Just would like to clarify that the JTAG server programming is having problem on the board but the on-board USB Blaster is working fine?

    Speaking about board reflashed/restored/reset, do you want to program MAX V with default hardware programming file? If it so, you may find the programming file available in Arria 10 SX SoC Package Installer. It is located in directory “..\arria10_10as066n3f40_soc_v15.1.2\examples\max5\PRD”.

    Thank You.

    Regards,

    YL

    • JET60200's avatar
      JET60200
      Icon for Contributor rankContributor
      6 years ago

      Hello ,

      ​

      Is it possile to get the the source code of system max V ( only binary system_max5.pof exists in Dev Kit), which uses to control the power sequence for the Arria 10 SoC Dev Kit ?

      We're working on a customer design with A10Soc , and they want to use MAX V as well on their customer board.

      Any way to get ? Thanks a lot

  • GPisc's avatar
    GPisc
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi everybody,

    My board is ARRIA 10 SoC Development Kit

    I'm trying to compile the vector_add example following the instructions in intelFPGA_pro/18.1/hld/examples_aoc/vector_add/README.html . One of the parameter is " -board=<board>",so it should be a10soc but the only available boards are a10gx. Tried to install the board using the aocl install and happens the next error.

    root@gabriel:/home/carol/intelFPGA_pro/18.1/hld/examples_aoc/vector_add# aocl install

    Do you want to install /home/carol/intelFPGA_pro/18.1/hld/board/a10_ref? [y/n] n

    Please specify a board package root to install:

    /home/carol/intelFPGA_pro/18.1/hld/board/a10soc

    aocl install: Adding the board package /home/carol/intelFPGA_pro/18.1/hld/board/a10soc to the list of installed pckages

    aocl install: Setting up FCD

    Warning: 'mmdlib' is not defined in /home/carol/intelFPGA_pro/18.1/hld/board/a10soc/board_env.xml.

    Unable to set up FCD. Please contact your board vendor or see section "Linking Your Host Application to the Khronos ICD Loader Library" of the Programming Guide for instructions on manual setup.

    --------------------------------------------------------------------

    Warning: No board installation routine supplied.

    Please consult your board manufacturer's documentation or support

    team for information on how to properly install your board.

    --------------------------------------------------------------------

    root@gabriel:/home/carol/intelFPGA_pro/18.1/hld/examples_aoc/vector_add# aocl diagnose

    /home/carol/intelFPGA_pro/18.1/hld/board/a10soc/arm32/bin/diagnose: 1: /home/carol/intelFPGA_pro/18.1/hld/board/a10soc/arm32/bin/diagnose: Syntax error: word unexpected (expecting ")")

    --------------------------------------------------------------------

    Warning:

    No devices attached for package:

    /home/carol/intelFPGA_pro/18.1/hld/board/a10soc

    --------------------------------------------------------------------

    /home/carol/intelFPGA_pro/18.1/hld/board/a10soc/arm32/bin/diagnose: 1: /home/carol/intelFPGA_pro/18.1/hld/board/a10soc/arm32/bin/diagnose: Syntax error: word unexpected (expecting ")")

    --------------------------------------------------------------------

    Call "aocl diagnose <device-names>" to run diagnose for specified devices

    Call "aocl diagnose all" to run diagnose for all devices

    How can i solve it ?? or which is the correct procedure to install the a10soc board and compile the examples ??

    Thanks

    gpd