Forum Discussion

LFang7's avatar
LFang7
Icon for New Contributor rankNew Contributor
6 years ago
Solved

How can I simulate dedicated high speed clock input pins in HyperLynx by FPGA's IBIS model?

Hi,

I download EP4SE530's IBIS model, but I can not find the dedicated high speed clock input pins in the model. The pin name is CLK[1,3,8,10]. So how can I simulate dedicated high speed clock input pins in HyperLynx by FPGA's IBIS model?

Yours,

Longyu

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    6 years ago
    Hi Fang Longyu, There is no dedicated IBIS model for these pin. Since the I/O Standard in Intel PSG FPGA is programmable, you may use the I/O standard that you choose for that input clock pin as the IBIS model. Example: if you use 2.5V I/O standard, you can use 2.5Vcmos IBIS model. Regards, YL

1 Reply

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Fang Longyu, There is no dedicated IBIS model for these pin. Since the I/O Standard in Intel PSG FPGA is programmable, you may use the I/O standard that you choose for that input clock pin as the IBIS model. Example: if you use 2.5V I/O standard, you can use 2.5Vcmos IBIS model. Regards, YL