How am I inferring latch in this code?

I'm getting warning 10631 in Quartus II (inferring latches)

Warning (10631): VHDL Process Statement warning at U6D2CPUSeq.vhd(947): inferring latch(es) for signal or variable "RST_RSMRST_N_200MS_DELAY", which holds its previous value in one or more paths through the process

Warning (10631): VHDL Process Statement warning at U6D2CPUSeq.vhd(947): inferring latch(es) for signal or variable "RST_RSMRST_N_200MS_CNT", which holds its previous value in one or more paths through the process

here is my code:

process(LED_500HZ_CLK,  RST_RSMRST_PLD_R_N_T,  RST_DEDI_BUSY_PLD_N)
begin
	if RST_RSMRST_PLD_R_N_T = '0' or RST_DEDI_BUSY_PLD_N ='0' then    
		RST_RSMRST_N_200MS_DELAY <= '0';
		RST_RSMRST_N_200MS_CNT 	 <= (others =>'0');
	elsif rising_edge(LED_500HZ_CLK) then
		RST_RSMRST_N_200MS_CNT <= RST_RSMRST_N_200MS_CNT + '1'; 
		if RST_RSMRST_N_200MS_CNT = "1100100" then    								
			RST_RSMRST_N_200MS_DELAY <='1';
		end if;
	end if;
end process;