New ContributorHi, can anyone explain what test input vector does? im a total beginner in FPGA, im using De1- SoC for comparing partial tmr and tmr fault tolerance. first time posting here, so idk how to ask question in the forum, sorry in advance
module tiv (clk_50, reset, start, again, c22, c23,
clk, i, pass, fail);
input clk_50, reset, start, again, c22, c23;
output clk, i, pass, fail;
reg clk = 1'b0;
reg [4:0]i;
reg s = 1'b0;
reg cond = 2'b00;
reg pass = 1'b0;
reg fail = 1'b0;
wire clk_out;
slowclock clock (clk_50, reset, clk_out);
always@(posedge clk_out) begin
clk = ~clk;
if (again) begin
clk = 1'b0;
s = 1'b0;
cond = 2'b00;
pass = 1'b0;
fail = 1'b0;
i = 5'b00000;
end
else begin
if (s) begin
case (cond)
2'b00: begin
i = 5'b00000;
if (c22 == 1'b0 && c23 == 1'b0) begin
cond = 2'b01;
i = i + 1;
end
else fail = 1'b1;
end
2'b01: begin
if (c22 == 1'b0 && c23 == 1'b0) begin
if (i == 5'b11111) pass = 1'b1;
else i = i + 1;
end
else fail = 1'b1;
end
endcase
end
else begin
if (start) s <= 1;
else s <= s;
end
end
end
endmodule
