Forum Discussion
AAzri1
New Contributor
New ContributorHi, can anyone explain what test input vector does? im a total beginner in FPGA, im using De1- SoC for comparing partial tmr and tmr fault tolerance. first time posting here, so idk how to ask question in the forum, sorry in advance
module tiv (clk_50, reset, start, again, c22, c23, clk, i, pass, fail); input clk_50, reset, start, again, c22, c23; output clk, i, pass, fail; reg clk = 1'b0; reg [4:0]i; reg...
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi @AAzri1 ,
Test input vector / stimulus are the inputs to your design/ DUT. Used to check the functional behavior of the design.
There are basically few testbench each have its own advantages and disadvantages.
- Simple testbench
- Self-checking testbench
- Self-checking testbench with testvectors
Work on above mentioned testbench.
Check below links
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf
https://www.youtube.com/watch?v=qZNL1C0TwY8
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Best Regards,
Anand
I have not checked your code
