Hai All, I m doing my project in FPGA SRAM based Ternary content addressable memory. How can I include ternary bit (don't care -x) during verilig and vhdl coding

'X' as a signal value is not supported in synthesis. Only '0' and '1' are.

So if you want to have a data element represent three unique states (0, 1, X) you need to use 2 bits and encode the values (ie, 00=>0, 01=>1, 1X=>X).

So however much memory you were planning on using, basically double that value.

Hi Sisira,

X is Non-Synthesizable, Z is only synthesizable on IO pads.

One of the tasks of the designer is to provide correct reset sequences to bring the model into a known state, without 'x'.

Regards

Anand