Hai All, I m doing my project in FPGA SRAM based Ternary content addressable memory. How can I include ternary bit (don't care -x) during verilig and vhdl coding

Hi Sisira,

X is Non-Synthesizable, Z is only synthesizable on IO pads.

One of the tasks of the designer is to provide correct reset sequences to bring the model into a known state, without 'x'.

Regards

Anand