Hi Team, We tried to check the jic file programming setup in Cyclone v gt eval board. For that we have created the system in FPGA design like this:nios ii reset and exception vector parameter:firmware code structure we have followed like this:linker script and other parameters in bsp editor:make target->mem_init gen used to create hex file.JIC File conversion parameters setup:with this jic, we have programmed the fpga, Our expected output from this is 3 led should blink( 1 controlled by FPGA DESIGN and other2 controlled by firmware code).But with jic programming, firmware controlled led is not blinking.But in .elf file programming, firmware controlled led is blinking.do we miss anything? Please guide us to resolve this.

Hello, This is to let you know I am investigating your case. I will get back to you once I have the solution for your issue. regards,Farabi

Hi,With your Exception Vector (RAM IP settings) set to OCRAM, you need your BSP as follows:Re-build the BSP and project, and re-generate the new .hex using the "mem_init_generate" tools.Replace your .hex with this new .hex (with above BSP settings) in Platform Designer and create your new .jic and re-try.

Hi Eberlazare, I have tried with the settings you have mentioned in above response, with that also firmware controlled led is not working.the setting which i have used:and i have one doubt that two hex files are generated in mem_init folder, i am using epcq hex file only for generating the jic file programming. Is that correct only right?

Hi,I think it is because of your Reset Vector offset in your first post, for EPCQ, you need to have offset address for your application as the .jic will also have the .sof at 0x0, so you do not want to overlap it. Anyway, you can find the info here:https://www.intel.com/content/www/us/en/docs/programmable/683689/current/reset-and-exception-vector-settings.htmlYou can determine the minimum reset vector offset by using the following equation:minimum reset vector offset= (.sof image start address + .sof image size) in HEXYou can also try as per the document, set the Reset Vector offset to "0x01E00000". With that, you need to regenerate the Platform Designer to get the new ".sopcinfo" file and use it to create the new BSP and project. To confirm you have the Reset Vector offset changed, you can view them when you add in the ".hex" when you try to create the ".jic" file:

Hi, We have tried as per the steps you have mentioned in previous response. But relative address is not reflecting in the jic file generation.reset vector offset is changed in nios ii parameter settings ,hex data parameter is we have tried with this , but firmware part is not working. Can you please guide us to resolve this as we have less time to give commitment to customer.

FW_CODE_NOT_WORKING_WHEN_CONFIGURED_FPGA_WITH_JIC_PROGRAMMING

15 Replies

Farabi
Regular Contributor
2 years ago
Hello,

This is to let you know I am investigating your case.
I will get back to you once I have the solution for your issue.

regards,
Farabi
EBERLAZARE_I_Intel
Regular Contributor
2 years ago
Hi,
With your Exception Vector (RAM IP settings) set to OCRAM, you need your BSP as follows:
Re-build the BSP and project, and re-generate the new .hex using the "mem_init_generate" tools.
Replace your .hex with this new .hex (with above BSP settings) in Platform Designer and create your new .jic and re-try.
- SERMASWATHIKA
  Contributor
  2 years ago
  Hi Eberlazare,
  I have tried with the settings you have mentioned in above response, with that also firmware controlled led is not working.
  the setting which i have used:
  and i have one doubt that two hex files are generated in mem_init folder, i am using epcq hex file only for generating the jic file programming. Is that correct only right?
  - EBERLAZARE_I_Intel
    Regular Contributor
    2 years ago
    Hi,
    I think it is because of your Reset Vector offset in your first post, for EPCQ, you need to have offset address for your application as the .jic will also have the .sof at 0x0, so you do not want to overlap it. Anyway, you can find the info here:
    https://www.intel.com/content/www/us/en/docs/programmable/683689/current/reset-and-exception-vector-settings.html
    You can determine the minimum reset vector offset by using the following equation:
    minimum reset vector offset= (.sof image start address + .sof image size) in HEX
    
    You can also try as per the document, set the Reset Vector offset to "0x01E00000".
    
    With that, you need to regenerate the Platform Designer to get the new ".sopcinfo" file and use it to create the new BSP and project.
    
    To confirm you have the Reset Vector offset changed, you can view them when you add in the ".hex" when you try to create the ".jic" file:
Farabi
Regular Contributor
2 years ago
Hello,

Just to let you know that I am checking your case. will get back to you as soon as possible.

regards,
Farabi
Farabi
Regular Contributor
2 years ago
Hello,

I am sorry, I am replacing previous Application Engineer as he is no longer with us.
Can you try to follow this guide: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/nios-ii-processor-booting-from-cfi-flash.pdf

regards,
Farabi
- SERMASWATHIKA
  Contributor
  2 years ago
  Hi Farabi,
  Ok, we will check and let you know.
  i have checked the document which you have shared.
  In that configuration, passive parallelx16 is mentioned,
  but eval board which we are having is cyclonve v gt eval. In that manual , configuration is active serial mode
  Is that ok to use the programming setup in this eval board?
Farabi
Regular Contributor
2 years ago
Hello,

Yes, of course you can use the AS(Active Serial) mode as your configuration.
AS mode is simpler, as it is directly programmed the flash from JTAG via FPGA.

regards,
Farabi
Farabi
Regular Contributor
2 years ago
Hello,

I have provide the answer, I will transfer this case to community now.
If you have new question, please raise another ticket. We will be happy to help.

regards,
Farabi