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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

FW_CODE_NOT_WORKING_WHEN_CONFIGURED_FPGA_WITH_JIC_PROGRAMMING

Hi Team, We tried to check the jic file programming setup in Cyclone v gt eval board. For that we have created the system in FPGA design like this: nios ii reset and exception vector param...
Board Debug
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

With your Exception Vector (RAM IP settings) set to OCRAM, you need your BSP as follows:

Re-build the BSP and project, and re-generate the new .hex using the "mem_init_generate" tools.

Replace your .hex with this new .hex (with above BSP settings) in Platform Designer and create your new .jic and re-try.

SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

Hi Eberlazare,

I have tried with the settings you have mentioned in above response, with that also firmware controlled led is not working.

the setting which i have used:

and i have one doubt that two hex files are generated in mem_init folder, i am using epcq hex file only for generating the jic file programming. Is that correct only right?