Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFrame reader initialization
Hello,
I know there is already a lot on the forum about the Frame reader from the VIP suite, but I still don't get it running. I used the memtest software example to test the DDR Ram module of my Cyclone III Nios II evaluation kit (LCD 800 x 480 pixels) and it worked perfectly, so the harware design seems OK. I've implemented a Frame reader in the design (the same design with the test pattern generator works perfectly, so I think it must be the C-code for the initialization that contains some errors...). I want the LCD to display a complete white image, but the screen stays black. Here is the main.c file:#include <stdio.h># include <unistd.h># include <stdlib.h># include <string.h># include <ctype.h># include "system.h"# include <stdio.h># include <io.h>
typedef struct
{
unsigned int framebuffer;
}display_buffer;
int main(void)
{
display_buffer buffer;
//Make a White background
int xctr=0, yctr=0;
for( xctr=0; xctr<800; ++xctr ) {
for( yctr=0; yctr<480; ++yctr ) {
buffer.framebuffer = 0xFFFFFFFF;
}
}
//Frame 0 base adress
IOWR(ALT_VIP_VFR_0_BASE, 4, &buffer.framebuffer);
//Select frame 0
IOWR(ALT_VIP_VFR_0_BASE, 3, 0);
//number of words for frame 0 (800*480)=384 000
IOWR(ALT_VIP_VFR_0_BASE, 5, 384000);
//color cycles for frame 0 (800*480)
// see http://www.alteraforum.com/forum/showthread.php?t=20596&page=2
IOWR(ALT_VIP_VFR_0_BASE, 6, 384000);
// Frame 0 Reserved
IOWR(ALT_VIP_VFR_0_BASE, 7, 0);
//Frame 0 width
IOWR(ALT_VIP_VFR_0_BASE, 8, 800);
//Frame 0 Height
IOWR(ALT_VIP_VFR_0_BASE, 9, 480);
// Frame 0 Interlaced
IOWR(ALT_VIP_VFR_0_BASE, 10, 0);
//Start Frame Reader
IOWR(ALT_VIP_VFR_0_BASE, 0, 1);
printf("Frame reader initialized");
while(1);
return 0;
}
18 Replies
Altera_ForumI know it's perhaps a very stupid mistake I made, but maybe it would help if I added the complete project as a ZIP file, so here it is.
Thanks again! Best, Hans- Altera_Forum
Hi, it's me again. Have you tried using the SP2 for Quartus? There could be a patched FrameReader in the SP. Perhaps this solves the issue that the IRQ is not working correctly. I could not try it here at work, because we still use an older version.
If I find some time (perhaps to the weekend) I will test some more, somehow this issue don't let me go. Have a nice day! - Altera_Forum
For everyone who is interested, we discussed the issue and I think there are four possible error sources:
1. The interrupt of the FR does not work in SP 1 or earlier correct, so you will have to add a patch to the Reader. 2. Perhaps there are some TimingProblems in the Design. 3. The Frame Reader uses burst reads. So the DDR SDRAM Bridge does not support them in the configuration. Perhaps the video stream is running out of data because of this. 4. The implementation in the Nios EDS could be wrong. Perhaps the addressing of the buffer is not correct. Would be nice if anyone could prove or dissaprove some of this issues or add to the list. Thanks. - Altera_Forum
Hi, have you got the link to the post where you found it? Thanks.
- Altera_Forum
Yep, here it is!
http://www.alteraforum.com/forum/showthread.php?t=19710 - Altera_Forum
I do not have the time right now, to look into the example, but I tried this yersterday at my testing.
I have attached a picture of the modifications I made to the SOPC-system. I added a FrameBuffer, which I configured to use the same read burst and master bit width to access the DDR SDRAM in the design as your FrameReader. As I run this system on the neek it worked quite fine and gave me the testpattern. I had also configured the FrameBuffer to not add or throw away frames, so normally if the stream would have run out of the specification I expected the LCD image to be altered, too. I am curious what you get out of the project when you carry over the design from the example you found. - Altera_Forum
Hey,
Thanks again for the reply, I will test the example in my project as soon as I can, but I had to format my entire PC to setup a RAID system, and now NIOS IDE seems to have some troubles finding the include files in the Altera.components folder. So it will take some time until I'm completely up and running again. But I'll post when I got some results! Best, Hans - Altera_Forum
Hi Hans,
sorry but I think the design example you found will not bring you any further with your problem. I had some time yersterday evening and looked into the example and your code again. I then decided to put that all aside and program an example from scratch. So I started with the "standard" design example from the Nios Evaluation Kit CD v8.0 and implemented FrameReader and Output to the LCD by using the LCDVideoSyncGenerator. With a bit of tweaking after my first try (I typed one declaration wrong) I had a design. I then created some NIOS Code where I have read back the written data to be able to verify, that all registers and Ram is set right. This example works well, except the problem I had with some of my projects before, that the LCD is flickering heavily. (mixing VIP with VideoSyncGenerator => Avalon Video Protocoll vs. Avalon Protocoll) I then also tried to implement the IP Core using the Clocked Video Output in my new created design, but then I got no output at all. Then also I ran out of time, because even I must sleep sometimes ;-) I took your first code of experiment5 again and replaced the CVO against one LCDVideoSyncGenerator. I really expected that to work. I created a new Nios Project and used my code from the other now running project. in the bsp Editor I edited everything, so that the whole code is run and stored in the ssram. Unfortunately I got nothing out of your design again, perhaps there is some fault in the pinning or anything like that. Feel free to further investigate this issue, I have attached my testsystem to this thread for you. I thought once more about it and I think you could try to implement the CVO together withe the FrameReader. Perhaps there was just something with the pinning not right, as I tested the system, because my verilog is not so good. Good luck, yours Peet. (Please be aware, it's a RAR-File although the fileextension says .zip) - Altera_Forum
Hey Peet,
Thanks for the example design. I studied it for a few hours today but I must confess that I don't get NIOS IDE to Run it properly... I never get an image, the programs says the "Program running, wait!" line, and then it sort of dies. I have a feeling it has something to do with the include paths (altough the project builds properly, I saw you have a drivers directory and a HAL directory included in your bsp directory). But I have no real clue (the NEEK is fine, because I see the ALTERA logo every time I start it up ;) ) what that problem could be (I'm not a specialist in NIOS or Eclipse, I must confess) On the other hand I have some good news for the hardware, after looking at your SOPC project, I noticed that you configured the FR to output 3 color planes in parallel, and I saw the configuration of the VCO, which also had the parallel option on. I would change this to 3 planes in sequence (in the VCO and FR), because the VCO just outputs the data in the same format he gets it in, when it's parallel he outputs parallel data, when it's a sequens, he outputs a sequens. And the MAX II chip expects sequential data. I tested this with a standard TPG -> CVO setup and the symbols prooved my theory. My new theory I cannot test because I can't get the standard program to run properly... I have a bit of a feeling that I really let you down by having such stupid problems (why I cannot run your software properly...) although I tried every tutorial Altera is offering on their website... I'm really sorry for that. Thanks again for all your help! Best, Hans - Altera_Forum
Or it could have to do with the settings of the linker script. I use an auto generated in NIOS IDE and all settings (Program memory, ...., Heap, stack) are set to ddr_sdram which is probably also not the way it should be...
Best, and sorry again! Hans
