Hello I'm trying to read and write from and to HPS SDRAM on Agilex 7 boardI have this configuration of fpga2hps interface:On the other side I have two msgdma ip cores for MM to Stream and Stream to MM transfers. But MM to Stream DMA doesnt work as its busy bit is permanently set to 1. As I understood from reading the forum it can be related to fpga2sdram bridge which is not initialized right.So my question is:1) how to make sure my fpga2sdram bridge is in the right condition2) what can be wrong with the MM to Stream DMA?DMA settings:FPGA to HPS AXI bus state:

Hi,For the mSGDMA IP core, you can refer to the Embedded Peripherals IP UG:https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/modular-scatter-gather-dma-core.htmlFor the bridge setup, please refer here for the full documentation on what you can do:https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilexIf you have further questions on the setup, let me know.

Hi,Do you have any further questions?

Hello! Thank you for your answer. I've been able to run my fpga design, and it seems there was something wrong with u-boot.The problem now is that when I run my board with Linux booted from SD card fpga design doesn't work and the system hangs when I try to read or write to FPGA memory space. But somehow when I make U-boot not able to read FPGA bitstream from the SD card and do reboot everything works completely fine. I use HPS boot first config, so my bitstream is located on SD card. To summarize the process:1. Boot system as usual, FPGA will be programmed.2. go to /run/media/mmcblk0p1/ directory where FPGA bitstream is located3. rename fpga bitstream to any name, just to make sure u-boot won't find it4. reboot system and you will see that U-Boot wasn't able to program FPGAFailed to load 'fpga_bitstream.rbf' FPGA not ready. Bridge reset aborted!5. wait until system boot is over, loginNow after these steps I can use FPGA.For building SD card image I've used this linkhttps://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7?erpm_id=12888127_ts1687163227736It seems something is wrong after FPGA programming and it can be fixed by something U-Boot does before programming FPGA. I've tried to add more bridge enableor bridge disablecommands to CONFIG_BOOTCOMMAND but that didn't help. I use the latest commit of socfpga_v2022.10 branch in u-boot-socfpga repository.

Hi,Thanks for the info, I may need some time to digest it and I will get back to you.Just to be sure again, you can do read/write to FPGA in Linux environment, if you do not configure the FPGA in U-boot in prior boot stage?

Yes, but at this moment FPGA should be already configured in the previous boot.

FPGA to HPS bridge on Agilex 7

22 Replies

EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

Apologies for the late responds, in the doc I provided last time, it mentioned at the most bottom page, we do need to disable all bridges in U-boot if we have enabled them manually, before booting to the kernel, there is an issue with the RBO server currently, you may access it another time and confirm:
https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilex

I guess that demonstrate the behavior you're seeing? Do you see any other issue if you manually disable the bridges, every time your enabled it in U-boot?
Mikhail_a
Occasional Contributor
3 years ago
Hello.
Unfortunately I didn't find any document you told you provided before. Could you please send it one more time?
I tried to disable bridges in U-boot cmd console but without any success. Could you please provide the exact algorithm that can solve that issue?
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

The link is currently down:
https://www.rocketboards.org/foswiki/Projects/SettingUpAndUsingBridgesOnAgilex

There is something else I need to re-check, let me get back to you.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

The rocketboards link is still down, also I found this KDB that might have relation with your issue:
https://www.intel.com/content/www/us/en/support/programmable/articles/000094603.html

Can you try to apply the git patch and see if that would fix your issue without renaming/removing the .rbf to be configured?
Artavazd
New Contributor
3 years ago
Hello!

Thank you for your answer. Unfortunately this article handles the problem with FPGA2HPS but I have a problem with HPS2FPGA. Anyways I will update ATF to the latest version and try it.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

I believe the initial issue was the FPGA2HPS bridge, could you open a new thread regarding the new issue you're facing and we will work on the new thread on your new issue.
Artavazd
New Contributor
3 years ago
Hello,
You are right. Lets finish this thread. Thank you.
Artavazd
New Contributor
3 years ago
Sorry that was me but from another account. We can close this thread.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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FPGA to HPS bridge on Agilex 7

22 Replies

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