FPGA on DE0-Nano accessing the EPCS64

I believe I wrote that comment because for some lame reason Quartus won't let you synthesize a design if you have "Active Serial" mode selected as the configuration mode and your design has logic that accesses the EPCS pins. So that comment applies to the Quartus setting, rather than the actual hardware level implementation. Of course, my recollection might be wrong, in that it might be PS mode that is the problem (since in PS mode, DCLK becomes fixed as an input).

Let me go and check ...

Cheers,

Dave

Here's what I just did using the files in the zip you linked to;

1. Open scripts/constraints.tcl and uncommented the EPCS pin assignments

2. Open src/de0_nano.vhd and uncommented the ports on the entity and the output signal assignments (near the end of the file)

3. Started Quartus 12.1sp1, and sourced the synthesis script using the Tcl console. This produces the error messages

Info (169141): DATA dual-purpose pin not reserved
Error (169187): Following feature(s) of I/O pin epcs_csN has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location D2
	Info (169189): I/O feature 'Current Strength' has an invalid setting. The setting should be Default.
Error (169187): Following feature(s) of I/O pin epcs_sck has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location H1
	Info (169189): I/O feature 'Current Strength' has an invalid setting. The setting should be Default.
Error (169187): Following feature(s) of I/O pin epcs_mosi has invalid setting(s) in the configuration scheme ACTIVE_SERIAL when the pin is placed at pin location H2
	Info (169189): I/O feature 'Current Strength' has an invalid setting. The setting should be Default.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Error (171000): Can't fit design in device

This error is related to an invalid setting, so modify the constraints file so that the drive and slew rate settings are left at their default

#  -------------------------------------------------------------
#  EPCS
#  -------------------------------------------------------------
# 
#  The EPCS interface can only be used if the device is
#  *not* setup to configure in Active Serial mode.
# 
	set pin(epcs_csN)		{PIN = D2}
	set pin(epcs_sck)		{PIN = H1}
	set pin(epcs_mosi)		{PIN = H2}
	set pin(epcs_miso)		{PIN = C1}

the design will now synthesize correctly.

So my recollection above was backwards, in that it is PS mode that is the problem. To see that, do the following ...

4. Select Assignments->Device, Device&Pin Options, and select Configuration. Change the mode to Passive Serial, and then press the "Play" button in the Quartus GUI.

Info (169141): DATA dual-purpose pin not reserved
Error (176310): Can't place multiple pins assigned to pin location Pin_H1 (IOPAD_X0_Y22_N0)
	Info (176311): Pin epcs_sck is assigned to pin location Pin_H1 (IOPAD_X0_Y22_N0)
	Info (176311): Pin ~ALTERA_DCLK~ is assigned to pin location Pin_H1 (IOPAD_X0_Y22_N0)
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00

So PS mode does not allow you to define DCLK as an output, which makes sense, since an external configuration host is supposed to drive that pin.

Cheers,

Dave

I just looked at these files in my code versioning system, and they were already fixed, so I had fixed this in the original code a while back. I guess that is one of the downsides of having zip files available indefinitely on the web, as the bugs are indefinitely available too :)

Cheers,

Dave